Dispositivos semicondutores: diodos, transistores, tiristores, optoeletronica, circuitos integrados. Front Cover. Hilton Andrade de Mello. Livros Tecnicos e. 1 jun. MARQUES, Angelo Eduardo B.; CHOUERI JÚNIOR, Salomão; CRUZ, Eduardo César Alves. Dispositivos semicondutores: diodos e. Download as PDF or read online from Scribd. Flag for inappropriate content. Save. Dispositivos Semicondutores Diodos e Transistores. For Later. save. Related.
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Materiais e Componentes Semicondutores. Junctionless Nanowire Transistors Performance: Static and Dynamic Modeling. Effects of Substrate Orientation and Strain. A simulation study of self-heating effect dipositivos junctionless dispositvos transistors.
Gm-C chopper amplifiers for implantable medical devices. Universidade Federal do Rio Grande do Sul. Journal of Nanoelectronics and Optoelectronicsv. Static and dynamic compact analytical model for junctionless nanowire transistors. Solid-State Electronicsv. Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization.
Semiconductor Science and Technologyv. Temperature dependence of the electrical characteristics up to K of amorphous In-Ga-ZnO thin film transistors. Microelectronics and Reliabilityv. Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistors.
Charge-based compact analytical model for triple-gate junctionless nanowire transistors. Drain current model for short-channel triple gate junctionless nanowire transistors.
Semiconductor Science and Technology Printv. Junctionless transistires transistors operation at temperatures down to 4. Electronics Letters Onlinev.
Microelectronic Engineeringv. Double-gate junctionless transistor model including short-channel effects. Compact model for short-channel symmetric double-gate junctionless transistors. Journal of Integrated Circuits and Systems Ed. A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors. Trap density characterization dispositivod low-frequency noise in junctionless transistors.
Approximate analytical expression for the tersminal voltage in multi-exponential diode models. Analysis of the leakage current in junctionless nanowire transistors. Applied Physics Lettersv. An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices.
Transactions on Electron Devicesv. Cryogenic Operation of Junctionless Nanowire Transistor. An explicit multi-exponential model for semiconductor junctions with series and shunt resistances. Threshold voltage in junctionless nanowire transistors. Cryogenics Guildfordv. Microelectronics Luton Cessou em Journal of Integrated Circuits and Systemsv.
Microelectronics JournalOxford, Inglaterra, v. Transactions on Electron DevicesE. Impact of halo implantation on 0. Solid-State ElectronicsOxford, Inglaterra, v. High performance analog operation of double gate transistors with the graded-channel architecture at low temperatures.
Microelectronic EngineeringAmsterdan, Holanda, v. The Electrochemical Society Inc. The Electrochemical Society, The Electrochemical Society, Inc. Adaption of triple gate junctionless MOSFETs analytical compact model for accurate circuit design in a tranwistores temperature range. A fiodos method for junctionless transistors parameters extraction.
Shockley Semiconductor Laboratory
Self-heating-based analysis of gate structures on junctionless nanowire transistors. Analysis of p-type Junctionless nanowire transistors with different crystallographic orientations. Analysis of bulk and accumulation mobilities in n- and p-type triple gate junctionless nanowire transistors. Experimental comparative analysis between junctionless and inversion transistorws nanowire transistors down to 10 nm-long channel lengths.
Lateral spacers influence on the effective channel length of junctionless nanowire transistors. Analog performance of strained SOI nanowires down to 10K. A new series resistance extraction method for junctionless nanowire transistors. Physical insights on the dynamic response of junctionless nanowire transistors. Use of back gate dispositivod to improve the performance of n- and p-type UTBB transistors-based self-cascode structures applied to current mirrors.
Influence of the crystal orientation on the operation of junctionless nanowire transistors. From double to triple gate: Modeling junctionless nanowire transistors.
Improved analog operation of junctionless nanowire transistors using back bias. Ultra-low-power diodes using junctionless nanowire transistors. Effective channel length in Junctionless Nanowire Transistors. Effects of substrate orientation and strain. Proposal of compact analytical modeling for trigate junctionless nanowire transistors.
Analog operation of Junctionless Nanowire Transistors down to liquid helium temperature. Effect of the temperature on on Junctionless Nanowire Transistors electrical parameters down to 4K. Effective mobility analysis of n- and p-types SOI junctionless nanowire transistors. Improved continuous model for short channel double-gate junctionless transistors. SBMicro – Conference Proceedings.
European Space Agency Publications Division, ESA Publications Division, LATW Digest of papers, Halo Effects on 0. Livroo Temperature Operation of 0. Silicon-On-Insulator semiconduores and Devices X.
Livro dispositivos semicondutores diodos e transistores download – Google Docs
Proceedings of SBMicro, Proceedings of the International Conference on Microelectronics and Packaging, Journal de Physique IV. Rio de Janeiro, RJ, Proceedings of the 12th Microelectronics Student Forum, ligro Proceedings of Student Forum on Microelectronics, Proceedings of Student Forum on Microelectronics. Student Forum on Microelectronics, Porto Alegre. Student Forum on Microelectronics Abstracts of st Meeting of the Electrochemical Society, Fomentar a estada do Prof. Durante o desenvolvimento do projeto e nas estadas do Prof.
Como principais resultados esperam-se: Dentro desse contexto listamos os seguintes objetivos: Como objetivos temos realizar pesquisa e desenvolvimento em: Humberto de Alencar Castelo Branco, n.
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