74154 DATASHEET PDF

The NTE is a monolithic 4-line-toline decoder in a Lead DIP type The NTE is fully compatible for use with most other TTL and DTL circuits. MOS technology. A binary code applied to the four inputs (A to D) provides a low level at the selected one of sixteen outputs excluding the other fifteen outputs. SNN .. of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration.

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National Semiconductor

By using our site, you acknowledge that you have read and understand our Cookie PolicyPrivacy Policyand our Terms of Service. Will someone please explain the purpose of inverting the outputs 0 through 15 as well as the use the NAND gates here?

First, the inversion of the outputs simply means that the output is active low. That is, for an input ofthe 0 output is selected, and it is driven low.

4 Line to 16 Line Demultiplexer / Decoder

All the other ouputs stay high. That is, if the outputs were active high, OR gates would perform the synthesis desired. Since the ouputs are active low, NAND gates do the job. The active-low enable inputs allow cascading of demultiplexers over many bits. If you wanted to generate a 1 of demultiplexer, you could use 16 s looking at the 4 least significant bits, while a single would look at the 4 most significant bits, with one ouput going to each of the other 16 s.

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And why are there 2 of them, you ask? Rather than providing only a single enable, both pins are used.

This allows more flexibility in the logic functions available. Many TTL parts and older memory 744154 have active low enable inputs, so the active low outputs of this part can be connected directly to those inputs. There are probably two enable inputs because otherwise there would be two unused pins on the 24 pin package I don’t recall seeing 22 pin DIP packages.

The active-low output is just how the design for that specific decoder was carried out – there is also active-high varieties. As for the NAND gates, there is a function being implemented in which the gates are there to realize it.

If you want to know exactly what is going on then draw out the truth table, but it is unlikely their function will make much sense to you. By clicking “Post Your Answer”, you acknowledge that you have read our updated terms of serviceprivacy policy and cookie policyand that your continued use of the website is subject to these policies.

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So is it possible that both enables are hooked to a 2-input OR gate; this is just making use of the extra pins to make 24? According to the internal logic diagram on the datasheet, the G inputs are connected to a two-input AND gate with inverting inputs, whose output feeds one input of all the NAND gates that produce the outputs. Sign up or log in Sign up using Google. Sign up using Facebook. Sign up using Email and Password.

National Semiconductor – datasheet pdf

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